Fully On-chip Charge Pump with Reversion Loss Reduction

Abstract

[evdate 2008-05-01] Hong Kong University of Science and Technology President's Cup (Final Report) Fully On-chip Charge Pump with Reversion Loss Reduction Personal details of authors Name Student ID School Department Year of E-mail Study Address Kwan Kwok To SENG ECE 3 Leung San Yiu SENG ECE 3 Phone Number 18 Abstract The charge pump with conventional gate control strategy was investigated, reversion loss is noticed and an improved control strategy is proposed. The optimization procedure of the strategy is also presented. New strategy can attain better performance in various aspects. Compared to the conventional design with the same configuration, the new one consumes less power at no-load condition, attains a higher output voltage, lower input current, smaller output ripple voltage, and eventually achieves a higher efficiency. Moreover, with the consideration of reversion loss, the new charge pump is able to work with different loading more efficiently.

In this report, 1 charge pump with conventional gate control strategy (LCP 1), 4 charge pumps with new control strategy (LCP2, LCP3, LCP4, LCP5) are discussed. Firstly, the problem analysis of LCP 1 is presented, followed by proposed solution and 4 improved versions of charge pumps (LCP2, LCP3, LCP4, LCP5). Finally, layout of LCP5 using O.35/lm process is shown and post simulation result is also demonstrated. Acknowledgement Many people have helped shape this project. This project would not have succeeded without institutional support, especially the technology resources from HKUST, professors, TAs and classmates. Our thanks go to our supervisor, Dr. Ki Wing Hung, for his encouragement and support throughout the project. Our thanks also go to our TA, Su Feng, for sharing his experience and problem solving techniques to us. 1.1 Introduction For micropower applications, electronic devices inside the system need different input voltage or need a higher voltage that is higher than supply voltage. Therefore, a converter is needed for the electronic devices to operate effectively. Charge pump is a kind of DC - DC converter which use some form of switching device(s) to control the connection of voltages to the capacitor in order to step up the power supply voltage. Charge pumps can be used as LCD or white LED drivers, generating high bias voltages from a single low-voltage supply, such as a battery. This project proposes a fully on-chip charge pump design that achieves a higher set-up ratio compared to those which are already in use now. 1.2 Aim and Objectives The aim of the project is going to produce a high efficiency linear charge pump. In the first part of this project, analysis will be done on the conventional gate control linear charge pump, we have to find out the existing problems of this topology. In the second part, we will try to propose solution for the problems. Since the charge pump is going to be fully on-chip, thus parasitic capacitance is an essential factor that we should consider throughout the whole project. In the third part, layout will be done and followed by post-layout simulation; this is to prove our design in a more realistic way. At the end of this project, a three stage (4x) linear charge pump will be designed in 0.35)u process. 1.3 Design specifications Vdd 0.9 -1.2 V Technology 0.35)um Frequency 14.7MHz (at Vdd = 1.2V) Iload 50uA Vout ~3.5V (at Vdd = 1.2V)

Table 1.3.1: Design specifications Our design is a 3-stage (4X) charge pump with improved gate control strategy. This project is mainly linear single branched charge pump. The model file used in the hspice is the 0.35)um CMOS technology provided by Austriamicrosystems. At the beginning, we will use l.2V as the V dd input for the simulation. At the end of the project we will try to use lower so that to observe the simulation result as the circuit working at low voltage condition and improve our circuit for a range of Vdd input. We will also use 50uA current as loading current. 2.1 Conventional Gate Control Charge pump (LCP1) Power transistors Gate control circuits Fig. 2.1: LCP1 Fig. 5.1 shows a charge pump with gate control strategy. The major advantages of this strategy over the traditional Dickson charge pump and other NMOS charge pumps are, 1. It does not have significant diode drop across each stage, since the power transistors are all PMOS, which can be fully turned on and turned off with using the gate control circuits below them. So it is more suitable for low voltage application. 2. The power PMOS directly used the voltage levels within the charge pump.

Simulation ofLCP1 was done, and the result is summarized below,

Measured Parameters Value Vout noload / Vripple noload 4.29V / 127mV Iin noload 154uA Vout (Iload=50 uA) 3.15 V Iin (Iload=50 uA) 318 uA V ripple (Iload=50uA) 241mV Efficiency 41.2 % Table 2.1: Result of LCP1 The above table shows that Vout at no load condition was 4.29V, this value is far from the ideal Vout_noload(1.2x4=4.8V). This indicates that there is some unexpected loss of power inside the circuit other than negligible switching loss.

Wave Symbol Current 1 Reverver Current of LCP1 Time Clock signals of LCP1

Fig. 2.2: Current profile of power transistors of LCP1 Fig.5.2 is a plot of Ids profile of all power transistors against time, and also the phase change during the instant. It is shown that there is serious reverse current in LCP1, which is certainly unfavorable in charge pump circuit. Reverse peak current of 275uA was measured in the simulation. Below is the analysis of the cause of reverse current.

Fig. 2.3: Reverse current paths

Fig. 2.4: Node voltages of GC2 during transitions Take the second stage as an example, referring to Fig.5.3 and Fig.5.4, when switches from Vdd to Vss, Vout1 drops from 2Vdd to Vdd at the same time. VGC2in follows to decrease from 2Vdd to Vdd, while VGc2H, which is, still at gnd. Under this situation, before Vgs of the GC2's NMOS has dropped under Vtn, M2 will still be on, and current would flow from out2 back to out1 as shown in Fig.5.3, which contributes to the reverse current.

The reverse current will be stopped until one of the below situations is reached. 1. Vout2 = Youth by reverse current (charge redistribution) 2. rises to Vdd, and turn off GC2's NMOS, and so M2, (Vout1- V2) <Vtn)

In the next transition, switches from Vdd to Vss, Vout2 drops from 3Vdd to 2Vdd, and VGC2L, which is 2, also drops at the same time. Under this situation, M2 is turned on. This, again, causes reverse current. Moreover, the two transistors of the GC2 will be on, and causing feed through current from out2 to Vss, these unwanted current flows will stop until one of the below situations is reached. 1. Vout2 = Youth by reverse current (charge redistribution) 2. Vout2 = Vout1, as Vout1 is boosted up by 1 The above problems appear in all other stages, this highly deteriorates the driving capability of the charge pump and thus the efficiency of it. To conclude, it is shown that, the current flows back during the dead time of the clock signals. Although a trivial solution is to minimize the dead time of the 2 signals, the dead time might be affected by process variation and parasitic capacitance. As a result, it is difficult for us to estimate the dead time very accurately.

2.2 Improvement in driving sequence Non-overlapping clock (overlapping low) was implemented (Fig.1.2.1). The working principle is simple; 1 goes high while clock is low, 2 goes high while clock is high, and neither of them can be high together. Non-overlap time can be increased by adding delay on the feedback path [5].

As mentioned in the last part, we are targeting to eliminate the reverse current of charge pump with gate control strategy, and a detail analysis was also done to illustrate how reverse current is contributed in the charge pump. Apart from changing the node voltage of the gate control, we also need to consider the ON/OFF sequence of the transistors in the charge pump. With a suitable ON/OFF sequence, the circuit can achieve a non-overlapping scheme, so as to eliminate the reverse current.

If we regard all the transistors are switches, then 2 stages of a multi-stage linear charge pump can be simply drawn like this.

Vn = (n-1)Vdd ~ (n)Vdd}

Fig. 2.2.1: Intermediate node voltages of a multi-stage linear charge pump

The above figure generalized 3 intermediate node voltages of a multi-stage linear charge pump. S1 and S2 are two transistors represented by two switches, and S3 and S4, emulate the clock signal swing between Vss and Vdd.

Assume it is in steady state operation, at certain instance, Vn+l = Vn = (n)Vdd, to complete a transition of S4: Vss to Vdd and S3: Vdd to Vss. We need to ensure the followings: 1. S1 should be OFF before S4 switches up to Vdd, otherwise, reverse current will flow through S1 due to potential difference. 2. S2 should be ON only after S3 has dropped to Vss and S4 has risen up to Vdd, such that V n+1 > Vn+2, and the current flows in forward direction.

The whole process should be like this:

Fig. 2.2.2: Steps of phase transition 1 In the next clock transition, which is S4: Vdd to Vss and S3: Vss to Vdd.Vn+2 = Vn+1 = (n+1)Vdd. At this instance, S1 should be OFF in order to prevent reverse current flowing back to node n, and S2 should be ON. Moreover, we need to ensure the followings: 1. S2 should be OFF before S4 drops; otherwise, charges will flow backward due to potential difference. 2. S1 should be ON after S4 has dropped; otherwise, reverse current will flow from node n+1 to node n. The whole process should be like this,

Fig. 2.2.3: Steps of phase transition 2 To summarize the above analysis, the ON/OFF sequence of the switches should be,

Fig. 2.2.4: ON/OFF sequence of the 4 switches To conclude all the above mentioned concerns, we can simply say, to avoid reverse current, we need to switch off all power transistors whenever we have clock transition at the negative plate of the capacitors. So an overlapping-low clock should be used to switch the power transistors, while clock transition should be carried out within the dead time of the non-overlapping clock. We would like to have a set of non-overlapping clock (3, 4) change from 1 to 0 and 0 to 1 during the dead time. Therefore, we use A2, C signal to form 3, 4. We have designed the following circuit:

Fig. 2.2.5: Non-overlapping clock generation circuit

One set of non-overlapping clock (1, 2) control the level shifter and the other set of non-overlapping clock (3, 4) control the power transistor.

2.3 Proposed Design with reversion loss consideration (LCP5)

Fig. 2.3.1: LCP5

Moreover, the new clock sequence stated in 2.2 is applied. 1 and 2 is a pair of non-overlapping signals, whereas 3 and 4 are a set of clock which both toggles during the dead time of 1 and 2. As a result, we can ensure all the power transistors in the main chain are turned off whenever the capacitors are being boosted up or ramped down. Simulation was done, and the result is summarized below, Measured Parameters Value Vout noload / Vripple noload 4.66V / 23.9mV Iin noload 109.9uA Vout (Iload=50uA) 3.501 V Iin (Iload=50uA) 306.8uA Vripple (Iload=50uA) 220mV Efficiency 47.6% Table 2.3.1: Result of LCP5 1.2

Reverse current of LCP5 Clock Signals of LCP5

(TIME)

Fig. 2.3.2: Current profile of power transistors of LCP5 The above results of LCP5 shows it successfully accomplished the task of reducing reverse current, the according to the figure above, all the transistor can complete the charge sharing process within T/2, this proved that the transistors could be fully turned on as it was in other designs. Moreover, the peak reverse current of the charge pump during operation is only 41.8uA, which is only 15.2% of LCP1, and this certainly leads to higher overall power efficiency. Further improvement of LCP5 in terms of efficiency can be made if we only use one level shifter for each of the non overlapping phase 1 and 2 in the whole circuit, since they would be having a swing of V out and Vss. This, however, might lead to some other problems, such as the Vgs of the early stages will be too large that the process may not support. In addition, this increases switching loss inside the circuit.

2.4 Optimization of PMOS in LCP5 The PMOS size is very important to the performance of the circuit. If the transistors are too small, charge sharing will not be able to complete and causes the efficiency to drop; if the transistors are too big, the associated gate capacitance will be too large that switching loss will increase, so efficiency decreased again. Therefore, the sizes of these power transistors had to be carefully defined in order to take care of the above criteria. The optimization procedure can be done with steps below, (1) Define the Cfly, freq (2) Find optimal Ron with 2RonCCfly + Cparasitic) = T/2 (3) Find optimal W/L with Ron equation

Below is the optimization of calculation, an approximate value of optimal PMOS width is obtained. (1) Cfly= 10pF, Freq = 14.7MHz (2) R = 34ns = 1482 2x(1 0 pF + 1.468 pF) (3) Optimal W IL W = 1 =>W=19.5 0.35,u 24,u(1.2 - 0.6915)1482 jltn To further optimize the transistor size, from the circuit, the Vgs are actually between Vdd and 2Vdd except for PMOS at stage one, therefore, the size of PMOS of the later stages can be decreased. So, Optimal W/L for Vgs = 1.5vdd = 1.8V) W 1 =>W=8.9jltn 0.35,u 24,u(1.8 - 0.6915)1482 After the theoretical size is obtained, the simulation is then done with PMOS widths around the theoretical value, results were plotted in a graph of Efficiency against size of transistors, and after that, the transistor size is finalized.

Efficiency of LCP5 with different PMOS width PMOS width

Fig. 2.4.1: PMOS width from 16 um to 24 um Efficiency of LCP5 with different PMOS width(M1 =20um)

PMOS width

Fig. 2.4.2: PMOS width from 811m to 1611m (with Ml fixed at 20u) After the optimization step, including calculation and simulation, the optimal transistor sizes were confirmed, to maximize the efficiency, the PMOS of the later stages can be set at 12um. Yet, we can also set all the PMOS width at W=20um.

Comparing the two configurations, The Optimized LCP5 can attain an efficiency of 48%, while the original one has 47.5%. The trade off of this will be the decreased working range, it is predicted that the optimized LCP5 will have a steeper trend of efficiency decay along increasing loading current. A plot of efficiency against loading current of the two configurations is presented to show the difference.

Efficiency vs Ilaod (LCP5 and LCP5 Optimized) Iload(uA) Fig. 2.4.3: Efficiency vs Iload of LCP5 and LCP5_optimized 2.5 Optimization of PMOS in LCP5 From the above result, in order to achieve the highest efficiency, the PMOS transistor in the main chain should be having the size around 20llm when Vgs is approximately equals to Vdd. However, for LCP1, the PMOS size is determined by one more factor, which is reversion loss. Although large transistors would decrease the Ron and is important for large loading, it also introduces greater reversion loss. So in this regard, the PMOS width can only be l0um. As a result, it is foreseeable that incomplete charge sharing will occur earlier than LCP3, 4 and 5, thus implying that the effective loading range of LCP1 would be smaller.

Below is a graph showing the performance of LCP1 with PMOS W=10um and PMOS W=20um. It also shows that the working range of LCP1 is highly related to the transistor size, and results in a narrower effective working range.

Efficiency vs Iload (LCP1s) Iload (uA)

Fig. 13.2.1: Efficiency vs Iload of LCP1 with different PMOS widths 2.6 Optimization of Buffers Another set of power transistors worthy of our consideration is the pair of PNMOS under the flying capacitors. Since they are used to supply charges to the charge pump, with the effect of parasitic capacitance and also the power extra power consumption of the level shifters, it is predicted that these pairs of PNMOS should be larger than the PMOS of the main chain. First of all, as they are connected in a way as an inverter, it is necessary for us to employ a pair non-overlapping signals to turn the PNMOS on and off, otherwise, great shoot through current will exist and deteriorate the efficiency of the charge pump. With our new clock generator, 1, 3 and 2, 4 are actually the pairs of sequence that we proposed to drive the PNMOS with. Four clock signals

Time (Iin) (TIME) clock 1 and clock 3 clock 2 and dock 4

Time (Iin) Fig. 2.6.1: How to employ the non-overlapping signals The above figure shows the four phases relationship, a pair of PNMOS can be driven by either 1- 3-pair or 2- 4-pair, in which, 1 and 2 serve for driving the NMOS while 3 and 4 serve for driving the PMOS, as a result, PMOS is turned off before NMOS is turned on and vice versa. After that, a matrix of LCP5 with different PNMOS width was simulated, result shows the optimal PNMOS pair should be Wpmos = 50um and Wnmos = 30um.

2.7 Physical Layout of LCP5 After Hspice simulation, layout of LCPS was done, the layout was done using cadence. The whole design was divided into five parts, 1. Clock Generator 2. Level Shifters 3. Gate Control circuits 4. Large Buffers 5. Flying capacitors and output stage loading capacitor Below is a summary about the layout details, Foundry Austriamicrosystems Technology 0.35um CMOS C35 process Number of metal layer used M1,M2,M3 Number of poly layer used P1, P2 Dimension (exclude pad) X = 286.2um, Y = 223.85um Time used 18 man-hours Table 2.7.1: Summary of layout details Physical layout of LCPS was successfully completed, Fig. 15.l shows the view of completed layout of LCP5. Fig. 2.7.1 Capture of layout 2.8 Post Layout Simulation of LCP5 After layout, Design Rule Check (DRC) and Layout versus Schematic (LVS) were performed properly. The final spice file of LCPS with all the parasitic capacitance was extracted. Approximately 300 parasitic capacitors ranging from 0.001fF to 1.47pF were extracted

The results of them are tabulated below, LCP1 LCP5 LCP5_postsim Vdd 1.2V 1.2V l.2V Freq 14.7 MHz 14.7 MHz 14.7 MHz Cflying a=0.147 10pF lOpF 10pF ~=0.001 Stages 3 stages (4x) 3 stages (4x) 3 stages (4x) PMOS size 10)lm 20)lm 20)lm lin noload ()lA) lS3.8)lA 109.9)lA 139.7 )lA Vout noload (V) 4.29V 4.66V 4.47V V ripple noload(m V) 127mV 23.9mV 24.9mV lin ()lA) 318)lA 306.8)lA 321.1 )lA Vout(V) 3.lS3V 3.S01V 3.211 V lout ()lA) SO)lA SO)lA SO)lA Vripple (mV) 241mV 220mV 218mV Efficiency (%) 41.2% 47.6% 44.S% Table 2.8.1: Comparison of LCP1, LCP5 and LCP5_postsim The efficiency of the LCP5 in post simulation has dropped to 44.5%, which is sti1l 8% higher than the efficiency of LCP1 in simulation. After analysis, the drop in efficiency between the LCPS and LCP5_postsim is mainly due to the transistor sizes of buffers and gate control circuits being too small, such that when parasitic capacitances were added, the response of the circuit is not high enough. As a result, it is estimated that, if the transistor sizes of the control circuits can be larger, or design with a lower frequency, the two results can be closer. Moreover, the performance of the new level shifter was deteriorated. This is also because of the parasitic capacitances associated with the two 1 pF capacitors. In order to show the performance more completely, the Simulations were performed in the following steps, 1. (0us – 6us) - No loading current, allowing the circuit to build up voltage 2. (6us - 6.5us) -loading current increases from 0uA to 50uA 3. (6.5us – 15us) -loading current keeps constant at 50uA Below is the simulated waveforms of LCP5_postsim (Green), LCPS (Red) and LCP1 (Blue),

Fig. 2.8.1: Simulation of Vout of LCP1, LCP5 and LCP5_postsim 3 Conclusion After comparing the quantitative results such as Vout, efficiency, Vripple, it is proven that LCP5 had solved the major problems of LCP1. Apart from numerical values, it also had several qualitative advantages, below is a summary of advantages, LCP1 LCP5 Efficiency V out Input Power V rippie

Working range narrower wider Design constraint

Exact PMOS size has to be used, to avoid both incomplete charge sharing and reversion loss

Wide range of PMOS size can be used without serious altering the efficiency, the only factor is to ensure complete charge sharing

Loading

Reversion loss will be larger on increasing loading, as larger PMOS size leads to larger reversion loss Reversion loss was greatly larger on increasing reduced, this indicates that this design is more suitable for large loading application, since a large PMOS can be used

Table 3.1: Summary on LCP1 and LCP5 Within the whole project, throughout several modifications on the conventional gate controlled charge pump, we are able to achieve designs with lower input power, higher output voltage, and thus higher efficiency gate controlled charge pump. With LCP1, having the simplest structure; and LCP3, having the widest range of operation point as the PMOS gate driving is largest; and LCP5, having the best efficiency among all the designs, the most suitable structure can be chosen according to individual specifications.

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